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This is the documentation for xc 1.0.1. The current documentation describes the newest version.

Architecture

xcc is a heterogeneous data-parallel compiler. One source, in xc or in C, becomes one executable that holds native code for the CPU and a kernel for every GPU API the target can reach. The program decides at run time, on the machine it runs on, which devices to use.

xc source .xc C source .c, through clang's front end One SSA IR front ends lower once; par blocks found and validated here Optimiser SSA passes, loops, vectorisation, devirtualisation CPU code arm64, x86-64, win64, wasm32; and 68000, arm9, banked 6502 (in-house assemblers) GPU kernels Metal (MSL) CUDA (PTX) Vulkan (SPIR-V) WebGPU (WGSL) One executable native code, embedded kernels, the par runtime; no GPU toolkit needed to build At run time the par runtime measures the CPU's threads, each GPU and any remote GPU, and keeps the fastest.

The parts

Section titled “The parts”
  • Front ends. xc has a hand-written recursive-descent parser; C is read through clang’s front end as LLVM IR before any LLVM optimisation, and xcc translates it into its own IR. Both lower to the same SSA intermediate representation.
  • Data-parallel extraction. Loops whose iterations are independent become par blocks, in three phases: acquisition of candidate loops, validation of each one, and run-time device-under-test measurement that picks the devices.
  • The optimiser. SSA passes over the shared IR: inlining, CSE, LICM, loop vectorisation for NEON, AVX2, AVX-512 and WebAssembly SIMD, guarded devirtualisation, idiom recognition and more.
  • GPU kernels. Every par block is printed as Metal Shading Language, PTX, SPIR-V and WGSL by xcc itself, and embedded in the executable: zero-dependency GPU inlining, with no GPU toolkit at build time.
  • Tiles, devices and the network. The runtime cuts a block into tiles and schedules them across every CPU core, GPUs from different vendors at once, and GPUs on other machines served by xcd: transparent, scalable network tiling.
  • CPU back ends. arm64, x86-64, Windows x64 and WebAssembly, with in-house assemblers, linkers and Mach-O, ELF and PE writers, so a build needs no system toolchain. The same back-end design reaches the Motorola 68000, 32-bit ARM and a banked 6502.

Self-hosting

Section titled “Self-hosting”

xcc is written in xc and compiles itself. A release is built three times over, the compiler building the compiler, and the second and third builds must be byte-identical before it ships.